MAX7042EVKIT-433+【PDF 11/17 页】EVAL KIT MAX7042

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308MHz/315MHz/418MHz/433.92MHz

Low-Power, FSK Superheterodyne Receiver

TO FSK

BASEBAND FILTER

AND DATA SLICER

IF

LIMITING

AMPS

PHASE

DETECTOR

CHARGE

PUMP

LOOP

FILTER

10.7MHz VCO

2.1mV/kHz

Figure 1. FSK Demodulator PLL Block Diagram

Mixer

A unique feature of the MAX7042 is the integrated image

rejection of the mixer. This device is designed to elimi-

nate the need for a costly front-end SAW filter in many

applications. The advantages of not using a SAW filter

are increased sensitivity, simplified antenna matching,

less board space, and lower cost.

The mixer cell is a pair of double-balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side

injection (i.e., f LO = f RF - f IF ). The image-rejection circuit

then combines these signals to achieve a typical image

rejection of approximately 45dB. Low-side injection is

required as high-side injection is not possible due to

the on-chip image rejection. The IF output is driven by

a source follower, biased to create a driving imped-

ance of 330 ? to interface with an off-chip 330 ? ceram-

ic IF filter. Note that MIXIN+ and MIXIN- are functionally

identical.

Phase-Locked Loop (PLL)

The PLL block contains a phase detector, charge

pump/integrated loop filter, voltage-controlled oscillator

(VCO), asynchronous 32x frequency divider, and crys-

tal oscillator. This PLL does not require any external

components. The relationship between the RF, IF, and

crystal reference frequencies is given by:

Intermediate Frequency (IF)

The IF section presents a differential 330 ? load to pro-

vide matching for the off-chip ceramic filter. The inter-

nal six AC-coupled limiting amplifiers produce an

overall gain of approximately 65dB. The limiting ampli-

fiers have a bandpass-filter-type response centered

near the 10.7MHz IF frequency with a 3dB bandwidth

of approximately 10MHz. The limiter output is fed into a

PLL to demodulate the IF, producing a baseband volt-

age with a demodulation slope of 2.1mV/kHz. The RSSI

circuit produces a DC output proportional to the log of

the IF signal level with a slope of approximately

16mV/dB.

FSK Demodulator

The FSK demodulator uses an integrated 10.7MHz PLL

that tracks the input RF modulation and determines the

difference between frequencies as logic ones and

zeros. The PLL is illustrated in Figure 1. The input to the

PLL comes from the output of the IF limiting amplifiers.

The PLL control voltage responds to changes in the fre-

quency of the input signal with a nominal gain of

2.1mV/kHz. For example, an FSK peak-to-peak devia-

tion of 50kHz generates a 105mV P-P signal on the con-

trol line. This control line is then filtered and sliced by

the FSK baseband circuitry.

The FSK demodulator PLL requires calibration to over-

come variations in process, voltage, and temperature.

f XTAL =

(f RF ? f IF )

32

The maximum calibration time is 120μs, which is includ-

ed in the startup time. Recalibration is necessary after a

significant change in temperature or supply voltage.

For additional information on proper crystal selection,

see the Crystal Oscillator and Frequency Tolerance

sections.

Calibration occurs automatically each time the

MAX7042 is powered up. Drive EN low and then high to

force a recalibration. EN must be driven from low to

high after the MAX7042 supply voltage is stable for

proper initial FSK calibration.

______________________________________________________________________________________

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